What it does in the chain
This link in one sentence
An analogy: an AI chip is like a fully fitted-out luxury apartment. NVIDIA is the architect who draws the blueprints (how to design the chip); but the ones who actually turn the blueprints into a building — and knock several units together into one sprawling open-plan home — are the leading-edge foundry and the advanced packaging house. This link is the AI chip's "construction and assembly shop." Many people assume that once a chip is designed, product exists — in fact, building and assembling it is the real bottleneck.
Getting a few terms straight
- GPU: a chip built for massively parallel computation, the main compute workhorse for AI training and inference. NVIDIA also designs its own companion CPU (a general-purpose processor that handles scheduling-type tasks) and DPU (a chip dedicated to networking, storage, and security that takes those chores off the GPU).
- Leading-edge process / leading-edge node: making chips with the newest, finest-featured process generation; the industry uses designations like N4, N3, N2 — the smaller the number, the more advanced and the harder to manufacture. Today virtually only TSMC can do this step well at scale.
- Packaging: after a chip "tapes out" (the first trial production run at the fab once design is complete), the main compute die, HBM (a high-speed memory that sits right next to the GPU — covered in detail in the next unit), and several other chips still have to be assembled at high density, wired together, and fitted with cooling to form a deliverable module — that step is advanced packaging, and it is far more than "putting on a case."
- CoWoS: TSMC's single most critical advanced packaging scheme. Simply put, the main GPU die and the HBM are "mounted" side by side on a silicon board packed with ultra-dense wiring (this board is the silicon interposer — essentially the expressway between chips), which then goes onto a high-end substrate (the ABF substrate). Because the chips are laid out flat and then stacked one more layer, the industry calls this "2.5D packaging." TSMC bundles the CoWoS, SoIC, and InFO packaging technologies into one family it calls 3DFabric.
Why this link matters from an investor's standpoint
One takeaway is enough: whether high-end AI accelerators can be built at all and delivered on time is often bottlenecked not by "design," but by this link's leading-edge process capacity + advanced packaging capacity. And it isn't decided by any single machine — it takes wafer fabrication, packaging, substrate, memory, and materials suppliers working as one coordinated set. This is a "systems integration" type of bottleneck that no one can break through at a single point. When reading a value chain, the key is not memorizing terms but seeing who delivers to whom, who gates whom, and who can charge whom.